Design chips from logic gates to layout
A technical internship in chip design covering digital electronics, CMOS technology, Verilog HDL, and the ASIC/FPGA design flow, with hands-on RTL and verification projects.
This program provides structured training in VLSI (Very Large Scale Integration) design, covering digital electronics fundamentals, CMOS technology, Verilog HDL programming, and RTL design and verification. In the third month, learners apply their skills to an individual project and a collaborative industry project, gaining exposure to synthesis, timing analysis, and the ASIC/FPGA design flow. The program prepares learners for roles such as RTL Design Engineer, Verification Engineer, and Physical Design Engineer through technical interview preparation and career guidance.
Pick the plan that fits your pace and goals.
Self Paced Program
₹6,000
What's included:
Intermediate Program
₹9,000
What's included: